1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to pull-up and pull-down circuitry for input/output pads of integrated circuits.
2. Description of Related Art
Integrated circuits include input/output (I/O) pads used for receiving and transmitting signals. During operation, if an I/O pad is left “floating”, meaning that the pad is not being driven to a known voltage by external or internal drivers, the pad may float at a voltage level sufficient to cause input buffer circuitry connected to the pad to turn-on and operate unpredictably. This unpredictable operation increases power consumption for the device and may cause damage to the input buffer circuitry. A floating voltage on the pad may also place the input buffer circuitry in an indeterminate state, resulting in indeterminate signals propagating to the internal circuitry of the device and causing oscillations and other spurious effects.
In order to avoid such issues, integrated circuits typically include pull-up or pull-down circuitry to bias the pad to a known voltage when the pad is left in a floating condition.
FIG. 1A is a schematic diagram of prior art input/output circuitry for a pad 105 of an integrated circuit device 100. The input/output circuitry includes input buffer circuitry 110, output buffer circuitry 120, and resistive weak pull-up circuitry 130.
Input buffer circuitry 110 has an input terminal 111 connected to the pad 105. The input buffer circuitry 110 includes a p-channel transistor 112 and an n-channel transistor 114, which act as a buffer to improve the signal integrity of the input signal applied to the pad 105. When a logic high voltage is applied to the pad 105, transistor 114 is turned off and transistor 112 is turned on, thereby coupling the supply voltage VDD to the output terminal 113 of the input buffer circuitry 110. When a logic low voltage is applied to the pad 105, transistor 114 is turned on and transistor 112 is turned off, thereby coupling the output terminal 113 to ground.
Thus, when operating properly, input voltage levels applied to the pad 105 by external sources are buffered by the input buffer circuitry 110, and the output terminal 113 of the input buffer circuitry 110 coupled to internal circuitry (not shown) provides the input signal for the integrated circuit device 100.
Output buffer circuitry 120 includes an input terminal 121 to receive an output signal from the internal circuitry of the integrated circuit device 100, and has an output terminal 122 connected to the pad 105. When an output enable signal is asserted, the pad is operated as an output pad and the output buffer circuitry 120 drives the pad 105 in response to the voltage level of the output signal. When the output enable signal is not asserted, the output 122 of the output buffer circuitry 120 is in a high-impedance “tri-state”.
During operation of the device 100, if the pad 105 is left to float, the voltage level on the pad 105 may cause pull-up transistor 112 and/or pull-down transistor 114 of the input buffer circuitry 110 to turn-on and conduct current. The floating voltage on the pad 105 can also place the output terminal 113 of the input buffer circuitry 110 into an indeterminate state, resulting in indeterminate signals propagating to the internal circuitry of the device 100. These indeterminate signals can cause oscillations and other spurious effects in the internal circuitry of the device 100.
If left floating, the voltage on the pad 105 may also cause both pull-up transistor 112 and pull-down transistor 114 to turn-on simultaneously, resulting in a significant cross-bar current flowing from VDD to ground through the transistors 112, 114. The cross-bar current can damage the input buffer circuitry 110 and cause failure of the device 100.
Thus in order to prevent a floating voltage on the pad 105, weak resistive pull-up circuit 130 is located between the pad 105 and the bias voltage VDD. The resistive pull-up circuit 130, consisting of a resistor or diode-connected transistor, biases the pad 105 to the bias voltage VDD when the pad 105 is not being driven by external or internal drivers. The pull-up circuit 130 is designed to be weak enough to be easily over-driven when the pad 105 is driven to a low voltage state by an external or internal driver. The resistive pull-up circuit 130 thus acts to prevent the pad 105 from floating and ensures that the input buffer circuitry 110 is in a known state when the pad 105 is not being driven by internal or external drivers. Alternatively, a resistive pull-down circuit 140 may be implemented as shown in FIG. 1B, to bias the pad 105 to ground when the pad 105 is not being driven.
One drawback to the use of resistive pull-up or pull-down circuits 130, 140 is that they consume significant amounts of power when the pad 105 is driven to a voltage level opposite that of the self-biased voltage level provided by the circuits 130, 140. Another drawback is that the current path through the resistive pull-up or pull-down circuits 130, 140 loads the pad 105 when the pad 105 is being driven by the output buffer circuitry 120, which impacts the output transient time of the device 100.
It is therefore desirable to provide improved pull-up and/or pull-down circuitry for pads of integrated circuits that minimize current consumption for the circuit and address the loading issues discussed above.